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MP8668
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8A, 21V, 600KHz Step-Down Converter with Synchronizable Gate Driver
The Future of Analog IC Technology
SPECIFICATIONS SUBJECT TO CHANGE - HUAWEI USE ONLY
DESCRIPTION
The MP8668 is a monolithic step-down switch mode converter with a built in internal power MOSFET. It achieves 8A continuous output current over a wide input supply range with excellent load and line regulation. Current mode operation provides fast transient response and eases loop stabilization. Fault condition protection includes cycle-by-cycle current limiting and thermal shutdown. The MP8668 requires a minimum number of readily available standard external components and is available in a space saving 3mm x 4mm 14-pin QFN package.
FEATURES
* * * * * * * * * * * * Wide 4.5V to 21V Operating Input Range 8A Continuous Output Current 42m Internal Power MOSFET Switch Power Good Indicator Synchronous Gate Driver Delivers up to 95% Efficiency Fixed 600KHz Frequency Synchronizable to >1MHz External Clock Cycle-by-Cycle Over Current Protection Thermal Shutdown Output Adjustable from 0.8V to 15V Stable with Low ESR Output Ceramic Capacitors Available in a 3mm x 4mm 14-Pin QFN Package Point of Load Regulator in Distributed Power System Digital Set Top Boxes Personal Video Recorders Broadband Communications Flat Panel Television and Monitors
APPLICATIONS
* * * * *
"MPS" and "The Future of Analog IC Technology" are Registered Trademarks of Monolithic Power Systems, Inc.
TYPICAL APPLICATION
VIN
4, 5, 6 IN BST 11
CB 10nF
12
Efficiency vs Load Current
100 95
EFFICIENCY (%)
VCC
SW
8, 9, 10
VIN=12V
VOUT 3.3V @ 8A M2
90 85 80 75 70 65 60 55 50 VOUT=3.3V 1 2 3 4 5 OUTPUT CURRENT (A) 6 VIN=20V
MP8668
2 PG BG 13
3.3V OFF ON
3
EN/SYNC GND 14
FB
1
MP8666 Rev. 0.91 1/22/2007
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MP8668 - 8A, 21V, 600KHz STEP-DOWN WITH SYNCHRONOUS www..com GATE DRIVER SPECIFICATIONS SUBJECT TO CHANGE - HUAWEI USE ONLY
PACKAGE REFERENCE
TOP VIEW
FB PG EN/SYNC IN IN IN N/C 1 2 3 4 5 6 7 14 13 12 11 10 9 8 GND BG VCC BST SW SW SW
ABSOLUTE MAXIMUM RATINGS (1)
Supply Voltage VIN ....................................... 23V VSW....................................... -0.3V to VIN + 0.3V VBS ....................................................... VSW + 6V All Other Pins................................. -0.3V to +6V Junction Temperature...............................150C Lead Temperature ....................................260C Storage Temperature ..............-65C to +150C
Recommended Operating Conditions
(2)
Supply Voltage VIN ........................... 4.5V to 21V Output Voltage VOUT ........................ 0.8V to 15V Operating Temperature .............-40C to +85C
EXPOSED PAD ON BACKSIDE
Thermal Resistance
Temperature -40C to +85C
(3)
Part Number* MP8668DL *
Package 3x4 QFN14
3x4 QFN14 ........................... TBD ... TBD . C/W
Notes: 1) Exceeding these ratings may damage the device. 2) The device is not guaranteed to function outside of its operating conditions. 3) Measured on approximately 1" square of 1 oz copper.
JA
JC
For Tape & Reel, add suffix -Z (eg. MP8668DL-Z) For RoHS Compliant Packaging, add suffix -LF (eg. MP8668DL-LF-Z)
ELECTRICAL CHARACTERISTICS
VIN = 12V, TA = +25C, unless otherwise noted.
Parameters Feedback Voltage Feedback Current Switch On Resistance (4) Switch Leakage Current Limit (4) Oscillator Frequency Fold-back Frequency Maximum Duty Cycle Minimum On Time (4) Under Voltage Lockout Threshold Rising Under Voltage Lockout Threshold Hysteresis EN Input Low Voltage En Input High Voltage EN Input Current Supply Current (Shutdown) Supply Current (Quiescent) Thermal Shutdown BG Driver Bias Supply Voltage Gate Driver Sink Impedance (4) Gate Driver Source Impedance (4) Gate Drive Current Sense Trip Threshold Power Good Threshold Power Good Threshold Hysteresis PG Pin Level
Note: 4) Guaranteed by design. MP8666 Rev. 0.91 1/22/2007 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. (c) 2007 MPS. All Rights Reserved.
Symbol Condition VFB 4.5V VIN 21V IFB VFB = 0.8V RDS(ON) VEN = 0V, VSW = 0V fSW tON VFB = 0.6V VFB = 0V VFB = 0.6V VFB = 1V
Min 0.790
Typ 0.810 10 42 0 600 150 90 100 4.1 800
Max 0.830
10
9.5 85
0.4 1.2 VEN = 2V VEN = 0V VEN = 0V VEN = 2V, VFB = 1V VCC RSINK RSOURCE 4.5 2 0 0 150 5 1 4 20 0.74 40 10 1.1 2 5.5
Units V nA m A A KHz KHz % ns V mV V V A A mA C V mV V mV V
VPG
PG Sink 4mA
0.4
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MP8668 - 8A, 21V, 600KHz STEP-DOWN WITH SYNCHRONOUS www..com GATE DRIVER SPECIFICATIONS SUBJECT TO CHANGE - HUAWEI USE ONLY
PIN FUNCTIONS
Pin # 1 Description Feedback. An external resistor divider from the output to GND, tapped to the FB pin sets the output voltage. To prevent current limit run away during a short circuit fault condition FB the frequency foldback comparator lowers the oscillator frequency when the FB voltage is below 250mV. Power Good Indicator. The output of this pin is low if the output voltage is less than 10% PG of the nominal voltage, otherwise it is an open drain. EN/SYNC On/Off Control and External Frequency Synchronization Input. Supply Voltage. The MP8668 operates from a +4.5V to +21V unregulated input. C1 is IN needed to prevent large voltage spikes from appearing at the input. N/C No Connect. SW Switch Output. Bootstrap. This capacitor is needed to drive the power switch's gate above the supply BST voltage. It is connected between SW and BST pins to form a floating supply across the power switch driver. VCC BG Driver Bias Supply. Decouple with a 1F ceramic capacitor. BG Gate Driver Output. Connect this pin to the synchronous MOSFET Gate. Ground. This pin is the voltage reference for the regulated output voltage. For this reason GND care must be taken in its layout. This node should be placed outside of the D1 to C1 ground path to prevent switching current spikes from inducing voltage noise into the part. Name
2 3 4, 5, 6 7 8, 9, 10 11 12 13 14
MP8666 Rev. 0.91 1/22/2007
www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. (c) 2007 MPS. All Rights Reserved.
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MP8668 - 8A, 21V, 600KHz STEP-DOWN WITH SYNCHRONOUS www..com GATE DRIVER SPECIFICATIONS SUBJECT TO CHANGE - HUAWEI USE ONLY
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VOUT = 2.5V, L = 2.2H, TA = +25C, unless otherwise noted.
Efficiency vs Load Current
VOUT = 3.3V 100 95 90
EFFICIENCY (%)
Hiccup with Output Short Circuit
VOUT = 3.3V VIN=12V
VOUT 1V/div. PG 5V/div. VSW 20V/div.
Power up
VOUT = 3.3V, No Load
85 80 75 70 65 60 55 50 1 2 3 4 5 OUTPUT CURRENT (A) 6 VIN=20V
VOUT 2V/div. VSW 10V/div. VIN 10V/div.
IL 5A/div.
IL 5A/div.
2ms/div.
Startup through Enable
VOUT = 3.3V, No Load
VOUT 2V/div.
Startup through Enable
VOUT = 3.3V, IOUT = 8A
Input Ripple Voltage
VOUT = 3.3V, IOUT = 8A
VOUT 2V/div. VSW 10V/div. VEN 10V/div. IL 5A/div. VSW 5V/div.
VSW 10V/div. VEN 10V/div. IL 5A/div.
VIN,AC 200mV/div.
2ms/div.
2ms/div.
Output Ripple Voltage
VOUT = 3.3V, IOUT = 8A
Load Transient Response
100 80
MAGNITUDE (dB)
Close Loop Bode Plot
100 80 Phase 40 20 Magitude 0 -20 -40 -60 -80 10k 100k -100
PHASE (degree)
60 40 20 0 -20 -40 -60 -80
60
VSW 5V/div.
VOUT,AC 200mV/div. VSW 10V/div.
VOUT, AC 20mV/div.
IOUT 5A/div.
-100 1k
MP8666 Rev. 0.91 1/22/2007
www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. (c) 2007 MPS. All Rights Reserved.
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MP8668 - 8A, 21V, 600KHz STEP-DOWN WITH SYNCHRONOUS www..com GATE DRIVER SPECIFICATIONS SUBJECT TO CHANGE - HUAWEI USE ONLY
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 2.5V, L = 2.2H, TA = +25C, unless otherwise noted.
Enabled Supply Current vs Input Voltage
0.45 0.40
INPUT CURRENT ( A) INPUT CURRENT (nA)
1150 1100 1050 1000 950 900
Disabled Supply Current vs Input Voltage
4.9 4.7 4.5
VCC (V)
VCC Regulator Line Regulation
0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0 5 10 15 20 INPUT VOLTAGE (V) 25
4.3 4.1 3.9 3.7 3.5 0 5 10 15 20 INPUT VOLTAGE (V) 25
0
5 10 15 20 INPUT VOLTAGE (V)
25
Case Temperature vs Output Current
40
CASE TEMPERATURE (OC)
Operating Range
NORMALIZED OUTPUT VOLTAGE
Load Regulation
1.001 VIN=20V 1.000 0.999 VIN=12V 0.998 0.997 0.996
VOUT = 3.3V
100
OUTPUT VOLTAGE (V)
VO_MAX SPEC
35 30 25 20 15 10 5 0 0 2 4 6 8 OUTPUT CURRENT (A) 10 0.1 0 5 10 15 20 INPUT VOLTAGE (V) 25 10
DMAX Limit 1.4MHz 1MHz
1
VFB_MIN 600KHz
0
1
2345678 LOAD CURRENT (A)
9 10
Line Regulation
IOUT = 8A
NORMALIZED OUTPUT VOLTAGE
1.002 1.001 1.000 0.999 0.998 0.997 0.996 0.995 5 7 9 11 13 15 17 19 21 INPUT VOLTAGE (V)
MP8666 Rev. 0.91 1/22/2007
www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. (c) 2007 MPS. All Rights Reserved.
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MP8668 - 8A, 21V, 600KHz STEP-DOWN WITH SYNCHRONOUS www..com GATE DRIVER SPECIFICATIONS SUBJECT TO CHANGE - HUAWEI USE ONLY
OPERATION
IN D
CURRENT SENSE AMPLIFIER
x40
REGULATOR
EN/SYNC
REGULATOR
OSCILLATOR 600KHz
S + -C1 1pF C1 50pF
CURRENT LIMIT COMPARATOR
Q
R R Q VCC SW VCC
DRIVER
VCC
REFERENCE
VBG FB
+ --
ERROR AMPLIFIER
PWM COMPARATOR
+ --
VBG
Figure 1--Functional Block Diagram The MP8668 is a fixed frequency, synchronous, step-down switching regulator with an integrated high-side power MOSFET and a gate driver for a low-side external MOSFET. It achieves 8A continuous output current over a wide input supply range with excellent load and line regulation. It provides a single highly efficient solution with current mode control for fast loop response and easy compensation. The MP8668 operates in a fixed frequency, peak current control mode to regulate the output voltage. A PWM cycle is initiated by the internal clock. The integrated high-side power MOSFET is turned on and remains on until its current reaches the value set by the COMP voltage. When the power switch is off, it remains off until the next clock cycle starts. If, in 90% of one PWM period, the current in the power MOSFET does not reach the COMP set current value, the power MOSFET will be forced to turn off. Error Amplifier The error amplifier compares the FB pin voltage with the internal 0.8V reference (REF) and outputs a current proportional to the difference between the two. This output current is then used to charge or discharge the internal compensation network to form the COMP voltage, which is used to control the power MOSFET current. The optimized internal compensation network minimizes the external component counts and simplifies the control loop design. Internal Regulator Most of the internal circuitries are powered from the 5V internal regulator. This regulator takes the VIN input and operates in the full VIN range. When VIN is greater than 5.0V, the output of the regulator is in full regulation. When VIN is lower than 5.0V, the output decreases. Since this internal regulator provides the bias current for the bottom gate driver that requires significant amount of current depending upon the external MOSFET selection, a 1uF ceramic capacitor for decoupling purpose is required.
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MP8666 Rev. 0.91 1/22/2007
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+ -BST
DRIVER
BG PG
POWER GOOD
GND
MP8668 - 8A, 21V, 600KHz STEP-DOWN WITH SYNCHRONOUS www..com GATE DRIVER SPECIFICATIONS SUBJECT TO CHANGE - HUAWEI USE ONLY Enable/Synch Control The MP8668 has a dedicated Enable/Synch control pin (EN/SYNC). By pulling it high or low, the IC can be enabled and disabled by EN. Tie EN to VIN for automatic start up. To disable the part, EN must be pulled low for at least 5s. The MP8668 can be synchronized to external clock range from 300KHz up to 1.4MHz through the EN/SYNC pin. The internal clock rising edge is synchronized to the external clock rising edge. Under-Voltage Lockout (UVLO) Under-voltage lockout (UVLO) is implemented to protect the chip from operating at insufficient supply voltage. The MP8668 UVLO comparator monitors the output voltage of the internal regulator, VCC. The UVLO rising threshold is about 4.0V while its falling threshold is a consistent 3.2V. Internal Soft-Start The soft-start is implemented to prevent the converter output voltage from overshooting during startup. When the chip starts, the internal circuitry generates a soft-start voltage (SS) ramping up from 0V to 1.2V. When it is lower than the internal reference (REF), SS overrides REF so the error amplifier uses SS as the reference. When SS is higher than REF, REF regains control. Over-Current-Protection and Hiccup The MP8668 has cycle-by-cycle over current limit when the inductor current peak value exceeds the set current limit threshold. Meanwhile, output voltage starts to drop until FB is below the Under-Voltage (UV) threshold, typically 30% below the reference. Once a UV is triggered, the MP8668 enters hiccup mode to periodically restart the part. This protection mode is especially useful when the output is dead-short to ground. The average short circuit current is greatly reduced to alleviate the thermal issue and to protect the regulator. The MP8668 exits the hiccup mode once the over current condition is removed. Thermal Shutdown Thermal shutdown is implemented to prevent the chip from operating at exceedingly high temperatures. When the silicon die temperature is higher than 150C, it shuts down the whole chip. When the temperature is lower than its lower threshold, typically 140C, the chip is enabled again. Floating Driver and Bootstrap Charging The floating power MOSFET driver is powered by an external bootstrap capacitor. This floating driver has its own UVLO protection. This UVLO's rising threshold is 2.2V with a hysteresis of 150mV. The bootstrap capacitor voltage is regulated internally (Figure 2). Even at no load condition, as long as VIN is 3V higher than VOUT, C4 will have enough voltage provided by VIN through D1, M1, C4, L1 and C2. If (VIN-VSW) is more than 5V, U2 will regulate M1 to maintain a 5V BST voltage across C4.
D1
VIN
M1 + 5V + -U2 -C4 VOUT SW L1 C2 BST
Figure 2--Internal Bootstrap Charging Circuit Startup and Shutdown If both VIN and EN are higher than their appropriate thresholds, the chip starts. The reference block starts first, generating stable reference voltage and currents, and then the internal regulator is enabled. The regulator provides stable supply for the remaining circuitries. Three events can shut down the chip: EN low, VIN low and thermal shutdown. In the shutdown procedure, the signaling path is first blocked to avoid any fault triggering. The COMP voltage and the internal supply rail are then pulled down. The floating driver is not subject to this shutdown command.
7
MP8666 Rev. 0.91 1/22/2007
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MP8668 - 8A, 21V, 600KHz STEP-DOWN WITH SYNCHRONOUS www..com GATE DRIVER SPECIFICATIONS SUBJECT TO CHANGE - HUAWEI USE ONLY
APPLICATION INFORMATION
Setting the Output Voltage The external resistor divider is used to set the output voltage (see the schematic on front page). The feedback resistor R1 also sets the feedback loop bandwidth with the internal compensation capacitor (see Figure 1). Choose R1 to be around 40.2k for optimal transient response. R2 is then given by:
R2 = R1 VOUT -1 0 .8 V
Synchronous MOSFET The external synchronous MOSFET is used to supply current to the inductor when the internal high-side switch is off. It reduces the power loss significantly when compared against a Schottky rectifier. Table 2 lists example synchronous MOSFETs and manufacturers. Table 2--Synchronous MOSFET Selection Guide
Part No. Si7112 Si7114 AM4874 Manufacture Vishay Vishay Analog Power
Table 1--Resistor Selection for Common Output Voltages
VOUT (V) 1.8 2.5 3.3 5 R1 (k) 40.2 (1%) 40.2 (1%) 40.2 (1%) 40.2 (1%) R2 (k) 32.4 (1%) 19.1 (1%) 13 (1%) 7.68 (1%)
Selecting the Inductor A 1H to 10H inductor with a DC current rating of at least 25% percent higher than the maximum load current is recommended for most applications. For highest efficiency, the inductor DC resistance should be less than 15m. For most designs, the inductance value can be derived from the following equation.
V x ( VIN - VOUT ) L = OUT VIN x IL x f OSC
Selecting the Input Capacitor The input capacitor reduces the surge current drawn from the input and also the switching noise from the device. The input capacitor impedance at the switching frequency should be less than the input source impedance to prevent high frequency switching current from pass to the input. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. For most applications, a 22F capacitor is sufficient. Selecting the Output Capacitor The output capacitor keeps output voltage small and ensures regulation loop stability. The output capacitor impedance should be low at the switching frequency. Ceramic capacitors with X5R or X7R dielectrics are recommended. PC Board Layout The high current paths (GND, IN and SW) should be placed very to the device with short, direct and wide traces. The input capacitor needs to be as close as possible to the IN and GND pins. The external feedback resistors should be placed next to the FB pin. Keep the switching node SW short and away from the feedback network.
Where IL is the inductor ripple current. Choose inductor current to be approximately 30% if the maximum load current, 8A. The maximum inductor peak current is:
IL(MAX ) = ILOAD + I L 2
Under light load conditions below 100mA, larger inductance is recommended for improved efficiency.
MP8666 Rev. 0.91 1/22/2007
www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. (c) 2007 MPS. All Rights Reserved.
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MP8668 - 8A, 21V, 600KHz STEP-DOWN WITH SYNCHRONOUS www..com GATE DRIVER SPECIFICATIONS SUBJECT TO CHANGE - HUAWEI USE ONLY External Bootstrap Diode It is recommended that an external bootstrap diode be added when the system has a 5V fixed input or the power supply generates a 5V output. This helps improve the efficiency of the regulator. The bootstrap diode can be a low cost one such as IN4148 or BAT54.
5V
BST
11
MP8668
SW 8, 9, 10
10nF
Figure 2--External Bootstrap Diode This diode is also recommended for high duty cycle operation (when
VOUT >65%) and high VIN
output voltage (VOUT>12V) applications.
MP8666 Rev. 0.91 1/22/2007
www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. (c) 2007 MPS. All Rights Reserved.
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MP8668 - 8A, 21V, 600KHz STEP-DOWN WITH SYNCHRONOUS www..com GATE DRIVER SPECIFICATIONS SUBJECT TO CHANGE - HUAWEI USE ONLY
PACKAGE INFORMATION
3mm x 4mm QFN14
2.90 3.10 PIN 1 ID MARKING 14 0.18 0.30 3.90 4.10 0.50 BSC 8 7 3.20 3.40 0.30 0.50 1.60 1.80 PIN 1 ID SEE DETAIL A 1
PIN 1 ID INDEX AREA
TOP VIEW
BOTTOM VIEW
0.20 REF
0.80 1.00 0.00 0.05
PIN 1 ID OPTION A 0.30x45 TYP.
PIN 1 ID OPTION B R0.20 TYP.
SIDE VIEW
DETAIL A
2.90 0.70 0.25 1.70
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX. 4) JEDEC REFERENCE IS MO-229, VARIATION VGED-3. 5) DRAWING IS NOT TO SCALE.
3.30 0.50
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications.
MP8668 Rev. 0.9 1/22/2007 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. (c) 2007 MPS. All Rights Reserved.
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